本文针对纳米小尺寸 CMOS 器件，提出了一种根据表面势模型表征热载流子产生电荷陷 阱和界面态局域分布的方法。热载流子注入 (Hot Carrier Injectione, HCI) 应力会在栅氧化层和 Si/SiO2 界面中产生电荷陷阱和界面态，随着应力时间递增，这些缺陷的增多引起阈值电压等器 件参数的漂移，在漏致势垒降低 (Drain Induced Barrier Lowering, DIBL) 效应下，可以选取表面 势最大值处的阈值电压偏移量来表征沟道相应位置处 HCI 致电荷陷阱和界面态。研究发现，通过 测量施加 HCI 应力前后器件阈值电压偏移量随源/漏极电压的分布，结合表面势模型计算出源/漏 极电压随沟道表面势峰值的分布，可以得到 HCI 致电荷陷阱和界面态沿沟道的局域分布。利用此 方法，精确地表征了在 32 nm CMOS 器件中 HCI 应力引起的电荷陷阱和界面态沿沟道的分布， 并进一步分析了 HCI 效应的产生机理。 

A surface potential technique is proposed to characterize the local distribution of hot-carrier-induced interface states and oxide charge in nanoscale CMOS devices. These defects are produced by the hot carrier injection stress in the Si/SiO2 interface and the gate oxide layer. With the increase of the stress time, the interface state and oxide charge will cause the drift of the device parameters such as the threshold voltage. Based on the DIBL effect, the threshold voltage offset at the peak of the surface potential is selected to characterize the number of HCI induced interface state and oxide charge at the corresponding position of the channel.The distribution of threshold voltage offset with source/drain voltage before and after HCI stress was measured. The local distribution of interface state and oxide charge numbers along the channel are obtained by surface potential model. In this paper, the distributions of interface state and oxide charge induced by HCI stress in 32 nm CMOS devices are accurately characterized, and the mechanism of HCI generation is analyzed.