A surface potential technique is proposed to characterize the local distribution of hot-carrier-induced interface states and oxide charge in nanoscale CMOS devices. These defects are produced by the hot carrier injection stress in the Si/SiO2 interface and the gate oxide layer. With the increase of the stress time, the interface state and oxide charge will cause the drift of the device parameters such as the threshold voltage. Based on the DIBL effect, the threshold voltage offset at the peak of the surface potential is selected to characterize the number of HCI induced interface state and oxide charge at the corresponding position of the channel.The distribution of threshold voltage offset with source/drain voltage before and after HCI stress was measured. The local distribution of interface state and oxide charge numbers along the channel are obtained by surface potential model. In this paper, the distributions of interface state and oxide charge induced by HCI stress in 32 nm CMOS devices are accurately characterized, and the mechanism of HCI generation is analyzed.